Integrated circuits (IC's) include input pads which receive external signals. Each input pad is typically connected to a corresponding input buffer circuit. FIG. 1 is a schematic diagram illustrating a typical input buffer circuit 100 which includes pull-up PMOS transistor 101, pull-down NMOS transistor 102, input pad 103 and internal input node 104. In response to the signal received on input pad 103, input buffer circuit 100 selectively connects internal input node 104 to a V.sub.CC voltage supply rail (i.e., a voltage supply rail which receives a first voltage, V.sub.CC, during normal operating conditions) or to a V.sub.SS voltage supply rail (i.e., a voltage supply rail which receives a second voltage, typically ground, during normal operating conditions).
Even if the V.sub.CC supply voltage has a voltage of 3.3 volts or less, it is desirable to allow a high input voltage (e.g., 5 volts) to be applied to input pad 103. However, when a high input voltage is applied to input pad 103, NMOS pull-down transistor 102 turns on. As a result, the source and drain of NMOS transistor 102 are each held at the V.sub.SS supply voltage (e.g., 0 volts), and the high input voltage is applied across the gate oxide of NMOS transistor 102. The high input voltage across the gate oxide of transistor 102 disadvantageously degrades the lifetime of the gate oxide of NMOS transistor 102.
One method used to solve this problem is to fabricate the gate oxide of each transistor on the IC to a thickness which is sufficient to withstand the applied high input voltage. However, such a thick oxide is typically not compatible with high speed advanced technology.
Another method is to form thick oxide transistors and thin oxide transistors on the same IC. Transistors required to receive high voltages are fabricated with a thick gate oxide. Conversely, transistors which are not required to receive high voltages are given a thin gate oxide to improve the speed of these transistors. However, this method disadvantageously increases process complexity.
It would therefore be desirable to have an input buffer circuit which is capable of receiving a high input voltage without experiencing degradation of gate oxide lifetime. It would further be desirable if such input buffer circuit does not reduce the operating speed of other transistors on the IC, or increase the complexity of the process used to fabricate the IC.